#include "timer.h"
#include "uart.h"
#include "usrlib.h"
TIMERCTR Timer3Ctr;
//Timer3	1ms 
void timer3_init(void)
{ 
  TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
	NVIC_InitTypeDef NVIC_InitStructure;
	
  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3  , ENABLE);
  TIM_DeInit(TIM3);                                             //
	
	NVIC_InitStructure.NVIC_IRQChannel=TIM3_IRQn;
	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=3;
	NVIC_InitStructure.NVIC_IRQChannelSubPriority=0;
	NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;
	NVIC_Init(&NVIC_InitStructure);
	
  //TIM3 configuration
	TIM_TimeBaseStructure.TIM_Prescaler = 720-1;                 		//
  TIM_TimeBaseStructure.TIM_Period = 100-1;                     	//
  TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;                //
  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;   //
  TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);
  
  TIM_ClearFlag(TIM3,TIM_FLAG_Update);                          //Clear TIM3 update pending flag
  TIM_Cmd(TIM3, ENABLE);                                        //TIM3 enable counter
  TIM_ITConfig(TIM3,TIM_IT_Update,DISABLE);                    	//Enable TIM3 Update interrupt
}



void uart1_tx_unlock_from_isr(void);
//Time3
void TIM3_IRQHandler(void)  //1ms
{
	uint16_t i;
	uint16_t bit;
	uint16_t Timer3CtrBit=0;
  if(TIM_GetITStatus(TIM3, TIM_IT_Update) != RESET)
  { 		
    TIM_ClearITPendingBit(TIM3, TIM_IT_Update);         //Clear TIM3 update interrupt
		DISABLE_INT();
		Timer3CtrBit=Timer3Ctr.devbit;
		ENABLE_INT();
		for(i=0,bit=1;i<16;i++,bit<<=1)
		{
			if(Timer3CtrBit&bit)
			{
				DISABLE_INT();
				if(Timer3Ctr.time[i]>0)
					Timer3Ctr.time[i]--;
				if(Timer3Ctr.time[i]==0)
				{
					Timer3Ctr.devbit &= ~bit;
					ENABLE_INT();
					switch(bit)
					{
// 						case UART1RXCTRBIT:
// 							USART_ITConfig(USART1, USART_IT_RXNE, DISABLE);
// 							xEventGroupSetBitsFromISR(EventGroup,BIT_UART1,&xHigherPriorityTaskWoken);
// 							if(xHigherPriorityTaskWoken!=pdFALSE)
// 							{
// 								portYIELD();
// 							}
// 						break;	
						case UART1TXCTRBIT:
							uart1_tx_unlock_from_isr();
						break;	
// 						case UART2RXCTRBIT:
// 							USART_ITConfig(USART2, USART_IT_RXNE, DISABLE);
// 							xEventGroupSetBitsFromISR(EventGroup,BIT_UART2,&xHigherPriorityTaskWoken);
// 							if(xHigherPriorityTaskWoken!=pdFALSE)
// 							{
// 								portYIELD();
// 							}
// 						break;	
// 						case UART2TXCTRBIT:
// 							xSemaphoreGiveFromISR(Binary_Uart2,&xHigherPriorityTaskWoken);
// 							if(xHigherPriorityTaskWoken!=pdFALSE)
// 							{
// 								portYIELD();
// 							}
// 						break;	
// 						case UART3RXCTRBIT:
// 							USART_ITConfig(USART3, USART_IT_RXNE, DISABLE);
// 							xEventGroupSetBitsFromISR(EventGroup,BIT_UART3,&xHigherPriorityTaskWoken);
// 							if(xHigherPriorityTaskWoken!=pdFALSE)
// 							{
// 								portYIELD();
// 							}
// 						break;	
// 						case UART3TXCTRBIT:
// 							xSemaphoreGiveFromISR(Binary_Uart3,&xHigherPriorityTaskWoken);
// 							if(xHigherPriorityTaskWoken!=pdFALSE)
// 							{
// 								portYIELD();
// 							}
// 						break;	
						#if 0
						case UART4RXCTRBIT:
							USART_ITConfig(UART4, USART_IT_RXNE, DISABLE);
							xEventGroupSetBitsFromISR(EventGroup,BIT_UART4,&xHigherPriorityTaskWoken);
							if(xHigherPriorityTaskWoken!=pdFALSE)
							{
								portYIELD();
							}
						break;	
						case UART4TXCTRBIT:
							xSemaphoreGiveFromISR(Binary_Uart4,&xHigherPriorityTaskWoken);
							if(xHigherPriorityTaskWoken!=pdFALSE)
							{
								portYIELD();
							}
						break;	
						#endif
					}
				}
				else
					ENABLE_INT();
			}
		}
		DISABLE_INT();
		if(Timer3Ctr.devbit==TIMER3RELEASE)
		{
			TIM_ITConfig(TIM3,TIM_IT_Update,DISABLE);
		}
		ENABLE_INT();
  }
}







